In today's high-frequency digital communication systems, a receiver typically recovers from the received data signal a “clean” data signal, from which processing circuitry can accurately recover the data carried by the signal. Many communication media such as metal wires (e.g., twisted pair), coaxial cables, PC board traces, or the atmosphere (i.e., wireless communications) are “lossy,” particularly at high frequencies. That is, these communication media degrade the signals that they carry, particularly the high-frequency components of these signals. A digital signal typically has relatively sharp transition edges, and thus typically includes signal components having relatively high frequencies. Consequently, in addition to attenuating a digital signal, a lossy communication medium may corrupt the phase of and/or smoothen the signal's transition edges, and one or more of these degradations may cause the processing circuitry to recover erroneous data from the signal. Therefore, in addition to amplifying the received digital signal, a high-frequency-digital-signal receiver typically re-sharpens the transition edges and reduces or removes the phase jitter from these edges to allow the processing circuitry to more accurately recover the data.
FIG. 1A is a block diagram of a conventional high-frequency digital communication system 10, and FIG. 1B is a diagram of a high-frequency digital signal 12 at three points (12a, 12b, 12c) within the system.
Referring to FIG. 1A, the system 10 includes a transmitter 14 for generating the digital signal 12a (FIG. 1B) on an output terminal 15, a lossy transmission medium 16 for carrying the transmitted digital signal, and a receiver 18 for receiving the degraded digital signal from the medium 16, for recovering a logic signal and the data carried by the logic signal, and for processing the recovered data. For example, the transmitter and receiver 14 and 18 may be two computers networked via the medium 16, which may be a PC board trace, fiber-optic or copper cable. The receiver 18 includes an input terminal 20 for receiving the degraded digital signal from the medium 16, and includes a sampler 22 for recovering a clean digital signal from the degraded digital signal. The sampler 22 includes a D flip-flop 24 having input and output nodes 26 and 28 and a clock node 30, and includes a circuit 32, which recovers a sample clock from the degraded data signal and provides the sample clock to the D flip-flop. The receiver 18 may also include pre-sampler circuitry 34, such as a preamplifier, input equalizer, or demodulator.
Referring to FIGS. 1A and 1B, the operation of the communication system 10 and the recovery of the clean digital signal by the sampler 22 is discussed. At the output terminal 15 of the transmitter 14, the data signal 12a has an amplitude A and relatively sharp transition edges 36. But the communication medium 16 degrades the signal such that at the input terminal 20 of the receiver 18, the amplitude of the degraded signal 12b is significantly lower than A, and the transition times of the edges 26 are reduced. Furthermore, the degraded signal 12b may include phase jitter that is not apparent in FIG. 1B. Fortunately, the sampler 22 generates a recovered digital signal 12c by effectively recovering from the degraded signal 12b the amplitude—the pre-sampler circuitry 34 may also assist with amplitude recovery, and the recovered amplitude may be other than A—the sharp edges 36, and the phase stability of the signal 12a. Specifically, the D flip-flop 24 has a trigger, i.e., detection, threshold. In response to each sampling edge—here the rising edge—of the sample clock, the flip-flop 24 generates on its output node 28 the recovered digital signal 12c having a logic 1 level if the amplitude of the degraded signal 12b at the flip-flop's input node 26 is higher than the detection threshold, and generates the recovered digital signal having a logic 0 level if the amplitude of the degraded signal is lower than the detection threshold. Consequently, the processing circuitry (not shown in FIG. 1A) can more accurately recover the data from the recovered signal 12c than it can from the degraded signal 12b. 
To optimize the accuracy with which the sampler 22 generates the recovered digital signal 12c, one may determine the characteristics of the degraded data signal 12b at the input terminal 20 of the receiver 18, and calibrate the sampler to these characteristics.
Referring to FIGS. 2A and 2B, one may characterize a data signal by the size and shape of its “eye.”
FIG. 2A is an eye pattern 40 of the data signal 12a of FIG. 1B at the output terminal 15 of the transmitter 14. The eye pattern 40 is the superposition of these data sequences back on itself over time, at its bit period The region 42 bounded by the rising/falling edges 36 is the eye opening of the pattern 40.
Similarly, FIG. 2B is an eye pattern 44 of the degraded data signal 12b of FIG. 1B at the input terminal 20 of the receiver 18. The region 46 bounded by the smoothened rising/falling edges is the eye opening of the pattern 44.
Referring to FIGS. 2A and 2B, one can see that the degradation (i.e., attenuation, transition-edge smoothening, and phase jitter) that the medium 16 imparts to the data signal 12a causes the eye 46 of the degraded data signal 12b to be significantly smaller both in voltage and in time than the eye 42 of the signal 12a. The thicker boundary of the eye pattern 44 is caused by amplitude and phase jitter. That is, the amplitude and phase jitter experienced by the degraded signal 12b causes multiple eye patterns to overlay one another at slightly different amplitudes and phases, thus making the signal-trace lines to appear thicker than those in FIG. 2A (the signal 12a experiences significantly less amplitude and phase jitter). Consequently, the thicknesses of the eye-pattern boundary are a rough measure of the ranges of the amplitude and phase jitter experienced by the degraded signal 12b. 
Still referring to FIGS. 2A and 2B, in mathematical terms, the eye pattern 44 represents the randomized distribution of the phase (time, i.e., the horizontal “X” dimension) and amplitude (amplitude, i.e., the vertical “Y” dimension) of the signal caused by noise and other degradation of the signal. More specifically, the eye opening 46 is bounded by randomized traces; and could be characterized as contours of varying probabilities. So one can characterize the pattern 44 in terms of probability of the trace lines passing to one side or another of a particular point when the signal represents a particular logic level. As an example, the point 47 away from the optimal center, is analyzed. When the signal represents a logic 1, at the rising edge of the sample clock (which is aligned to the point 47 in the X or time dimension), the probability that the trace line, and thus the signal amplitude, is greater than the detection threshold (which is aligned to the point 47 in the Y or voltage dimension) may be greater than 99%. Similarly, assuming a symmetrical system, when the signal represents a logic 1, at the rising edge of the sample clock the probability that the signal amplitude is less than the detection threshold is less than 1%. This indicates that less than 1% of the time, the sampling circuitry (not shown in FIGS. 2A and 2B) will erroneously characterize the sampled data. If this error rate is too high, then one can attempt to find another sampling point that provides a lower error rate. As discussed below, one typically attempts to determine the “optimum” sampling point that provides the lowest error rate. The optimum sampling point is often, but is not always, near the center point 48 of the eye 46. In this example, the bit-error-rate (BER) is effectively 1 in 100, or BER=10=2. In a typical communication system, the acceptable BER is well below 10−9.
Referring to FIGS. 1A and 2B, to generate the recovered digital signal 12c having the lowest error rate possible, one calibrates the sampler 22 to best match the characteristics of the eye pattern 44 of the degraded data signal 12b. Typically, one performs this calibration by adjusting the phase of the sample clock and the detection threshold of the D flip-flop 24 such that the sampling point 47, which is the intersection of the sampling edge—here the rising edge—of the sample clock and the sampling threshold, is as close as possible to the optimum sampling point, which in this example is the center of the eye 46. For illustration, consider the sampling point 47, which is not at the center of the eye 46. Because of relatively large (beyond that indicated by the eye-pattern traces in FIG. 2A) amplitude and phase jitter intermittently experienced by the degraded signal 12b the signal maybe above or below the threshold at point 47, thus giving rise to a possible errors in the recovered digital signal 12c. For example, if signal 12b is logically low, and jitter causes this signal to be temporarily located at a position above the sampling threshold of point 47, then the sampler 22 will erroneously generates the recovered digital signal 12c having a logic 1 level. Consequently, the farther the sampling point 47 is from the optimum sampling point 48 (here the center of the eye), the higher the chance of error in, and thus the higher the error rate of the recovered digital signal 12c. Conversely, the closer the sampling point 47 to the optimum sampling point 48 of the eye 46, the lower the chance of error in, and thus the lower the error rate of, the recovered data signal 12c. Furthermore, changes in the operating parameters (e.g., temperature) of the sampler 22 may shift the sampling point 47 farther from the optimum sampling point 48 of the eye 46. Therefore, to maximize the safety margin and thus to minimize errors in the recovered data signal 12c, one typically desires the sampling point 47 to be as close as possible to the optimum sampling point 48, which in this example is the center of the eye 46.
Unfortunately, measuring the eye 46 at the input terminal 20 of the receiver 18 and manually calibrating the sampler 22 in response thereto is wrought with many problems. For example, the eye 46 may be different than the eye (not shown) at the input node 26 of the D flip-flop 24, particularly where the receiver 18 includes the pre-sampler circuitry 34. Therefore, aligning the sampling point 47 with the center of the eye 46 at the input terminal 20 is no guarantee that the point 47 is also aligned with the center of the eye at the input node 26, and, thus, such alignment may not provide an acceptable error rate for the recovered digital signal 12c. Furthermore, the characteristics (e.g., shape, probability distribution) of the eye 46, the detect threshold of the flip-flop 24, and the phase of the sample clock may drift over time, thus requiring periodic manual recalibration of the sampling point 47. Or, noticeable drift may occur during operation of the receiver 18, and may thus increase the error rate of the recovered digital signal 12c. In a severe situation, the error rate may increase so much as to cause the receiver 18 to fail.
Still referring to FIGS. 1A and 2B, some manufacturers have proposed including in the receiver 18 circuitry (not shown) for measuring the eye of the degraded signal 12b at a node inside the receiver, and calibrating the sampler 22 according to this internal eye.
But this proposed solution has several limitations. For one, although this proposed circuitry within the receiver 18 measures the eye at a node that is electrically closer to the flip-flop input node 26 than the input terminal 20 is, this internal eye may still be different than the eye at the node 26. Furthermore, the proposed circuitry is single-ended, and thus cannot be incorporated in differential receivers. In addition, the proposed circuitry samples each degraded data signal to determine the boundary of the data eye. In many circumstances, this rate of sampling may be unnecessary, and thus a waste of power.